Audio
1. Overview
1.1 Rockchip Audio Features
This section describes the audio features of the RK platform, as shown in Table 1-1:
Table 1-1 Rockchip Audio Features
1.2 DAI
This chapter mainly describes the support of digital audio interfaces on the RK platform.
1.2.1 I2S
The RK platform has two types of I2S controllers: I2S and I2S-TDM. The I2S controller supports I2S and PCM protocols; the I2S-TDM controller supports I2S, PCM, and TDM protocols.
1.2.1.1 I2S Controller Features
- Supports 8-channel I2S protocol: standard, left justified, right justified
- Supports stereo PCM protocol: early, late 1, late 2, late 3
- Supports master/slave mode, mode applies to both TX/RX logic
- Supports 8k ~ 192k sampling rate, 384k sampling rate
- Supports 16 ~ 32 bits width
- Supports MSB/LSB mode
- Supports clock phase adjustment
- Supports clock compensation
Note:
384k sampling rate requires a high-precision clk, which can be imported from the MCLK PIN or use slave mode.
Mono PCM is not supported. If needed, stereo PCM can be used to transmit mono PCM, with valid data in slot 0.
Clock compensation is used for clock compensation in heterogeneous systems, such as UAC, but has usage restrictions. Refer to the audio clock compensation section.
1.2.1.2 I2S-TDM Controller Features
In addition to the functions supported by the I2S controller, the I2S-TDM controller adds the following features:
- Supports 8 slots TDM PCM protocol: normal, left shift mode[0~3]
- Supports 8 slots TDM I2S protocol: normal, left justified, right justified
- Supports configurable slot width: 16 ~ 32 bits
- Supports full mapping of data lines, can remap the relationship between data lines and paths
- Supports TX/RX asynchronous mode, independent clocks, can support independent sampling rates, bit widths, protocols
- Supports TX/RX synchronous mode, shared clock
- Supports configurable PCM FSYNC width: [1~7] sclk cycle or one channel block
- Supports configurable I2S FSYNC width: half frame / whole frame
Note:
Only even slot configurations are supported.
In TDM I2S long frame mode, up to 16 channels can be transmitted.
In TDM protocol, only path-0 is used, so when the physical PIN connected does not correspond to the channel, please remap the data line to path-0.
1.2.1.3 RK Series Chips I2S Support List
Chip | I2S | I2S-TDM |
---|---|---|
PX30/RK3326 | I2S1_2CH, I2S2_2CH | I2S0_8CH |
RK1808 | I2S1 | I2S0 |
RK3036 | I2S0 | |
RK3066 | I2S0, I2S1, I2S2 | |
RK312X | I2S_8CH, I2S_2CH | |
RK3188 | I2S0 | |
RK3288 | I2S0 | |
RK322X | I2S0, I2S1, I2S2 | |
RK3308 | I2S_2CH_0, I2S_2CH_1 I2S_8CH_0, I2S_8CH_1, I2S_8CH_2, I2S_8CH_3 | |
RK3328 | I2S0, I2S1, I2S2 | |
RK3368 | I2S_8CH, I2S_2CH | |
RK3399 | I2S0, I2S1, I2S2 | |
RK3568/RK3566 | I2S0_8CH, I2S1_8CH, I2S2_2CH, I2S3_2CH | |
RV1108 | I2S0, I2S1, I2S2 | |
RV1126/RV1109 | I2S1_2CH, I2S2_2CH | I2S0_8CH |
1.2.2 PDM
1.2.2.1 PDM Controller Features
The RK platform supports digital microphones or ADCs with PDM protocol. Specific features are as follows:
- Supports master mode only
- Supports up to 8 MIC array
- Supports 16 ~ 24 bits width
- Supports 8 ~ 48k sampling rate
- Supports channel swapping
- Supports high-pass filtering: 3.79 Hz, 60 Hz, 243 Hz, 493 Hz
- Supports storage alignment: left alignment, right alignment
- Supports full mapping of data lines
- Supports clock phase adjustment
- Supports clock compensation
Note: Storage alignment is only for formats with bit width greater than 16 bits. For formats greater than 16 bits, data is stored by word, with low bits padded with 0 by default. Clock compensation is used for clock compensation in heterogeneous systems, such as UAC, but has usage restrictions. Refer to the audio clock compensation section. Full mapping of data lines is only supported on RV1126 and later chips: RV1126/RV1109, RK3568/RK3566...
1.2.2.2 RK Series Chips PDM Support List
Chip | Name | Max Channel | Version |
---|---|---|---|
PX30/RK3326 | PDM | 8 | V2 |
RK1808 | PDM | 8 | V2 |
RK2108 | PDM | 4 | V3 |
RK3308 | PDM_8CH | 8 | V2 |
RK3328 | PDM | 8 | V1 |
RK3568/RK3566 | PDM | 8 | V3 |
RV1126/RV1109 | PDM | 8 | V3 |
Version Description
Version | Description |
---|---|
V1 | 1. Supports standard mode, corresponding clocks: 2.048/2.822/3.072 MHz. |
V2 | 1. Added fractional division. 2. Added storage alignment mode. |
V3 | BUG FIX: 1. Fixed sign bit overflow issue when HPF is enabled and input signal amplitude is close to 0 db. 2. Fixed passband ripple consistency issue, new version passband ripple is less than 0.1 db. 3. Fixed aliasing issue. Features: 1. Added low power mode, corresponding clocks 1.024/1.411/1.536 MHz. 2. Added high performance mode, corresponding clocks 4.096/5.644/6.144 MHz. |
1.2.3 DCODEC
The RK platform supports digital CODEC interface, which can be connected to analog CODECs supporting this protocol, such as RK812, to form a complete CODEC. In addition, when the controller works in DSM mode, it can drive an external PA to meet the needs of ordinary audio quality products and save costs.
- Supports 3-channel ADC
- Supports stereo DAC
- Supports asynchronous mode: playback and recording sampling rates can be different.
- Supports synchronous mode: playback and recording sampling rates must be the same.
- Supports PGA / ALC
- Supports DSM output, direct drive PA
- Supports high-pass filtering
1.2.4 VAD
Voice Activity Detection (VAD) receives data from DAI, processes and analyzes statistics, and triggers an interrupt to wake up the system when the preset threshold is reached. A brief data flow diagram is shown in Figure 1-1:
Figure 1-1 RK VAD Data Flow
- When the system is in sleep, DAI -> VAD -> SRAM remain working, VAD continuously receives data, filters, performs noise self-learning, and stores audio data in the SRAM circular buffer.
- When VAD detects that the sound exceeds the preset threshold, it generates an interrupt to wake up the CPU. The CPU turns off VAD. When VAD is turned off, the data flow automatically switches to the DMAC channel, i.e.: DAI -> DMAC -> DDR -> CPU standard recording path.
- The CPU seamlessly fills the data in SRAM into the recording buffer, and the data processing is transparent to user space.
- After waking up, the ASR program analyzes the recorded data, such as keyword detection.
1.2.5 SPDIF
The RK platform supports the SPDIF Transmitter interface protocol. In particular, the RK3308 also supports SPDIF Receiver.
- Supports 16 ~ 24 bits width
- Supports 192k sampling rate
- Supports stereo uncompressed audio, i.e. LPCM
- Supports 5.1 / 7.1 compressed audio, such as: DD, DD+
- Supports Optical, Coaxial
Note:
When outputting 192k sampling rate, an Optical device supporting 192k is required.
1.3 Combo DAI
The RK platform supports arbitrary combinations of DAIs to form Combo DAIs, as shown in Figure 1-2:
2. Audio Driver Development
This chapter describes the audio support, driver development, and debugging on the RK platform.
2.1 Basic Structure of Sound Card
This section introduces the basic structure of a sound card, as shown in Figure 2-1:
Figure 2-1 ALSA Sound Card Structure
DAI: Digital Audio Interface.
MACHINE: Link dai and codec to be a new sound card.
DMAENGINE: Transfer data between memory and dai's fifo.
In general, to add a sound card based on the released SDK, you only need to port or write a codec driver. In rare cases, you need to add a machine driver. See the Machine Driver Development section for details.
2.2 Code List
The code list and description are as follows:
kernel/sound/soc/rockchip$ tree -I "*.o|*.h"
.
├── rk3288_hdmi_analog.c
├── rk3399_gru_sound.c
├── rockchip_audio_pwm.c /* low quality audio out by driving pa */
├── rockchip_cdndp.c
├── rockchip_da7219.c
├── rockchip_hdmi_analog.c /* hdmi and codec share the same i2s */
├── rockchip_hdmi_dp.c /* hdmi and dp share the same i2s */
├── rockchip_i2s.c /* old i2s which support i2s/pcm */
├── rockchip_i2s_tdm.c /* new i2s-tdm which support i2s/pcm/tdm */
├── rockchip_max98090.c
├── rockchip_multicodecs.c /* support multi-streaming */
├── rockchip_multi_dais.c /* support combo-dais */
├── rockchip_multi_dais_pcm.c /* co-work with combo-dais */
├── rockchip_pcm.c /* audio data flow and control */
├── rockchip_pdm.c /* pdm dai driver */
├── rockchip_rt5645.c
├── rockchip_rt5651.c
├── rockchip_spdif.c /* spdif tx dai driver */
├── rockchip_spdifrx.c /* spdif rx dai driver */
├── rockchip_vad.c /* voice activity detection driver */
├── vad_preprocess_arm64.S /* vad preprocess algorithm for arm64 */
├── vad_preprocess_arm.S /* vad preprocess algorithm for arm32 */
└── vad_preprocess_thumb.S /* vad preprocess algorithm for thumb */
kernel/sound/soc/codecs$ tree -P "rk*.c|h*.c|d*.c"
.
├── dmic.c /* driver for dmic, e.g. i2s dmics, pdm dmics */
├── dummy-codec.c /* driver for dmic, direct, none-codec */
├── hdac_hdmi.c
├── hdmi-codec.c /* hdmi codec driver */
├── rk1000_codec.c
├── rk312x_codec.c /* internal codec */
├── rk3228_codec.c /* internal codec */
├── rk3308_codec.c /* internal codec 8ch adc */
├── rk3328_codec.c /* internal codec */
├── rk817_codec.c /* codec in rk817 pmic ic */
└── rk_codec_digital.c /* link with external analog part, e.g. rk812. */
2.3 DAI Driver Development
The DAI drivers in the released SDK are already complete. Developers only need to configure properties to enable the corresponding functions according to the application scenario.
2.3.1 I2S
2.3.1.1 Protocol Format Setting
The protocol format is set by the Machine Driver parsing the DTS, and then calling the set_fmt API to set the controller's protocol format. For Simple Card, refer to the Simple Card section.
2.3.1.2 Master / Slave Setting
Master / slave setting is done by the Machine Driver parsing the DTS, and then calling the set_fmt API to set the controller's protocol format. For Simple Card, refer to the Simple Card section.
2.3.1.3 Clock Phase Inversion Setting
Clock phase inversion is set by the Machine Driver parsing the DTS, and then calling the set_fmt API to set the controller's protocol format. For Simple Card, refer to the Simple Card section.
2.3.1.4 bclk-fs Setting
Property | Value | Description |
---|---|---|
rockchip,bclk-fs | int | By default, bclk is 64 times the sampling rate |
Example: bclk is 32 times the sampling rate
&i2s0 {
rockchip,bclk-fs = <32>;
};
2.3.1.5 High Precision Clock Setting
Property | Value | Description |
---|---|---|
rockchip,mclk-calibrate | boolean | Supports high-precision clock and clock compensation. For details, refer to Audio Clock Compensation |
2.3.1.6 Others
Property | Value | Description |
---|---|---|
rockchip,no-dmaengine | boolean | Do not bind dmaengine. For details, refer to Combo DAI Driver Development |
rockchip,playback-only | boolean | Only supports playback function, only registers TX DMA |
rockchip,capture-only | boolean | Only supports recording function, only registers RX DMA |
For more features, see the kernel documentation: kernel/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
2.3.2 I2S-TDM
In addition to the functions supported by the I2S controller, the I2S-TDM controller adds the following features:
2.3.2.1 TX/RX Clock Sharing Setting
Property | Value | Description |
---|---|---|
rockchip,clk-trcm | 0 | TX/RX logic is independent, each uses its own clock, there are two sets of clocks on the IO |
rockchip,clk-trcm | 1 | TX/RX logic is synchronous, sharing TX's clock, only TX's clock on IO |
rockchip,clk-trcm | 2 | TX/TX/RX logic is synchronous, sharing RX's clock, only RX's clock on IO |
Example: Set to share TX clock mode
&i2s0 {
rockchip,clk-trcm = <1>;
};
2.3.2.2 Data Line Full Mapping Setting
Hardware can connect to any data line, configure the corresponding property to correct the channel order.
Property | Value | Description |
---|---|---|
rockchip,i2s-tx-route | <int int int int> | Default is in order: SDO0 SDO1 SDO2 SDO3 |
rockchip,i2s-rx-route | <int int int int> | Default is in order: SDI0 SDI1 SDI2 SDI3 |
Example: Playback channel order is arranged as “SDO3 | SDO2 | SDO1 | SDO0”
&i2s0 {
rockchip,i2s-tx-route = <3 2 1 0>;
};
2.3.2.3 TDM Half Frame Mode Setting
Property | Value | Description |
---|---|---|
rockchip,tdm-fsync-half-frame | boolean | In TDM I2S mode, frame clock supports half-frame and long-frame formats, default is long-frame |
Example: Half-frame format
&i2s0 {
rockchip,tdm-fsync-half-frame;
};
2.3.2.4 TDM Slot Parameter Setting
The driver has implemented the set_tdm_slot interface. The Machine Driver parses the DTS property and then calls the set_tdm_slot API to set the corresponding parameters of the controller. For Simple Card, please refer to the Simple Card section.
For more features, see the kernel documentation: kernel/Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.txt
2.3.3 PDM
2.3.3.1 Data Line Full Mapping Setting
Hardware can connect to any data line, configure the corresponding property to correct the channel order.
Property | Value | Description |
---|---|---|
rockchip,path-map | <int int int int> | Default is in order: SDI0 SDI1 SDI2 SDI3 |
Example: Recording channel order is arranged as “SDI3 | SDI2 | SDI1 | SDI0”
&i2s0 {
rockchip,i2s-tx-route = <3 2 1 0>;
};
2.3.3.2 High Precision Clock Setting
Property | Value | Description |
---|---|---|
rockchip,mclk-calibrat | boolean | Supports high precision clock and clock compensation. For specific usage, refer to Audio Clock Compensation. |
2.3.3.3 Others
Property | Value | Description |
---|---|---|
rockchip,no-dmaengine | boolean | Do not bind dmaengine. For specific usage, refer to Combo DAI driver development. |
For more features, see the kernel documentation: kernel/Documentation/devicetree/bindings/sound/rockchip,pdm.txt