Audio
1. Overview
1.1 Rockchip Audio Features
This section describes the audio features of the RK platform, as shown in Table 1-1:
Table 1-1 Rockchip Audio Features
1.2 DAI
This chapter mainly describes the support of digital audio interfaces on the RK platform.
1.2.1 I2S
The RK platform has two types of I2S controllers: I2S and I2S-TDM. The I2S controller supports I2S and PCM protocols; the I2S-TDM controller supports I2S, PCM, and TDM protocols.
1.2.1.1 I2S Controller Features
- Supports 8-channel I2S protocol: standard, left justified, right justified
- Supports stereo PCM protocol: early, late 1, late 2, late 3
- Supports master/slave mode, mode applies to both TX/RX logic
- Supports 8k ~ 192k sampling rate, 384k sampling rate
- Supports 16 ~ 32 bits width
- Supports MSB/LSB mode
- Supports clock phase adjustment
- Supports clock compensation
Note:
384k sampling rate requires a high-precision clk, which can be imported from the MCLK PIN or use slave mode.
Mono PCM is not supported. If needed, stereo PCM can be used to transmit mono PCM, with valid data in slot 0.
Clock compensation is used for clock compensation in heterogeneous systems, such as UAC, but has usage restrictions. Refer to the audio clock compensation section.
1.2.1.2 I2S-TDM Controller Features
In addition to the functions supported by the I2S controller, the I2S-TDM controller adds the following features:
- Supports 8 slots TDM PCM protocol: normal, left shift mode[0~3]
- Supports 8 slots TDM I2S protocol: normal, left justified, right justified
- Supports configurable slot width: 16 ~ 32 bits
- Supports full mapping of data lines, can remap the relationship between data lines and paths
- Supports TX/RX asynchronous mode, independent clocks, can support independent sampling rates, bit widths, protocols
- Supports TX/RX synchronous mode, shared clock
- Supports configurable PCM FSYNC width: [1~7] sclk cycle or one channel block
- Supports configurable I2S FSYNC width: half frame / whole frame
Note:
Only even slot configurations are supported.
In TDM I2S long frame mode, up to 16 channels can be transmitted.
In TDM protocol, only path-0 is used, so when the physical PIN connected does not correspond to the channel, please remap the data line to path-0.
1.2.1.3 RK Series Chips I2S Support List
Chip | I2S | I2S-TDM |
---|---|---|
PX30/RK3326 | I2S1_2CH, I2S2_2CH | I2S0_8CH |
RK1808 | I2S1 | I2S0 |
RK3036 | I2S0 | |
RK3066 | I2S0, I2S1, I2S2 | |
RK312X | I2S_8CH, I2S_2CH | |
RK3188 | I2S0 | |
RK3288 | I2S0 | |
RK322X | I2S0, I2S1, I2S2 | |
RK3308 | I2S_2CH_0, I2S_2CH_1 I2S_8CH_0, I2S_8CH_1, I2S_8CH_2, I2S_8CH_3 | |
RK3328 | I2S0, I2S1, I2S2 | |
RK3368 | I2S_8CH, I2S_2CH | |
RK3399 | I2S0, I2S1, I2S2 | |
RK3568/RK3566 | I2S0_8CH, I2S1_8CH, I2S2_2CH, I2S3_2CH | |
RV1108 | I2S0, I2S1, I2S2 | |
RV1126/RV1109 | I2S1_2CH, I2S2_2CH | I2S0_8CH |
1.2.2 PDM
1.2.2.1 PDM Controller Features
The RK platform supports digital microphones or ADCs with PDM protocol. Specific features are as follows:
- Supports master mode only
- Supports up to 8 MIC array
- Supports 16 ~ 24 bits width
- Supports 8 ~ 48k sampling rate
- Supports channel swapping
- Supports high-pass filtering: 3.79 Hz, 60 Hz, 243 Hz, 493 Hz
- Supports storage alignment: left alignment, right alignment
- Supports full mapping of data lines
- Supports clock phase adjustment
- Supports clock compensation
Note: Storage alignment is only for formats with bit width greater than 16 bits. For formats greater than 16 bits, data is stored by word, with low bits padded with 0 by default. Clock compensation is used for clock compensation in heterogeneous systems, such as UAC, but has usage restrictions. Refer to the audio clock compensation section. Full mapping of data lines is only supported on RV1126 and later chips: RV1126/RV1109, RK3568/RK3566...
1.2.2.2 RK Series Chips PDM Support List
Chip | Name | Max Channel | Version |
---|---|---|---|
PX30/RK3326 | PDM | 8 | V2 |
RK1808 | PDM | 8 | V2 |
RK2108 | PDM | 4 | V3 |
RK3308 | PDM_8CH | 8 | V2 |
RK3328 | PDM | 8 | V1 |
RK3568/RK3566 | PDM | 8 | V3 |
RV1126/RV1109 | PDM | 8 | V3 |
Version Description
Version | Description |
---|---|
V1 | 1. Supports standard mode, corresponding clocks: 2.048/2.822/3.072 MHz. |
V2 | 1. Added fractional division. 2. Added storage alignment mode. |
V3 | BUG FIX: 1. Fixed sign bit overflow issue when HPF is enabled and input signal amplitude is close to 0 db. 2. Fixed passband ripple consistency issue, new version passband ripple is less than 0.1 db. 3. Fixed aliasing issue. Features: 1. Added low power mode, corresponding clocks 1.024/1.411/1.536 MHz. 2. Added high performance mode, corresponding clocks 4.096/5.644/6.144 MHz. |
1.2.3 DCODEC
The RK platform supports digital CODEC interface, which can be connected to analog CODECs supporting this protocol, such as RK812, to form a complete CODEC. In addition, when the controller works in DSM mode, it can drive an external PA to meet the needs of ordinary audio quality products and save costs.
- Supports 3-channel ADC
- Supports stereo DAC
- Supports asynchronous mode: playback and recording sampling rates can be different.
- Supports synchronous mode: playback and recording sampling rates must be the same.
- Supports PGA / ALC
- Supports DSM output, direct drive PA
- Supports high-pass filtering
1.2.4 VAD
Voice Activity Detection (VAD) receives data from DAI, processes and analyzes statistics, and triggers an interrupt to wake up the system when the preset threshold is reached. A brief data flow diagram is shown in Figure 1-1:
Figure 1-1 RK VAD Data Flow