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K3-CoM260 数据手册

60T 融合 AI 算力核心板

PDF 版本

版本​

版本日期修订说明
V1.22026.07.10更新供电要求及注意事项
V1.12026.07.09文档排版与表述优化
V1.02026.04.30首版

阅读指南​

本文档主要介绍 K3-CoM260 的基本规格和硬件特性，旨在帮助开发人员快速熟悉核心板规格，更准确高效地完成 K3-CoM260 应用及产品开发。

本文档主要适用于以下工程师：

  • 产品经理
  • 硬件工程师等

1. 产品介绍​

1.1 概述​

K3-CoM260 是进迭时空推出的首款金手指（Gold Finger）封装产品，集成 RISC-V AI CPU 芯片 K3、LPDDR5 芯片、GPHY 芯片和无源器件等。

K3-CoM260 支持多种操作系统和开发套件，包括进迭原生的 Bianbu 系统、Ubuntu 操作系统、Linux 和 OpenHarmony 等，配套 AI 全栈开发套件，能够满足 AI 多样化的开发需求。

K3-CoM260 提供了丰富的接口，涵盖 MIPI-DSI、MIPI-CSI、DP 1.2、SDIO 3.0、eSPI、SPI、I2S、I2C、CAN-FD、PWM、UART、USB 2.0、USB 3.0、PCIe 3.0、GMAC 等。凭借其高性能和丰富的接口资源，K3-CoM260 是 RISC-V 端侧应用方案和产品开发的更优选择。

1.2 产品特点​

  • 卓越的 CPU 性能

    8 个高性能计算大核 X100 结合 8 个 AI 核 A100，提供超过 130 KDMIPS 的 CPU 算力。X100 单核 SPECint2006 > 9.0/GHz，最大主频 2.4 GHz。

  • 同构融合 AI 算力 提供 60 TOPS AI 算力，以超宽并行计算的 AI 核提供强大的通用 AI 算力，实现与所有主流 AI 生态的快速对接，7B 本地大模型算力 > 10 Tokens/s。

  • 最新的 RISC-V 架构，超级并行计算能力 A100 支持高达 1024 bit 的 RVV 1.0 并行计算，支持最新的 RVA23 Profile 和 Vector Crypto 标准。

  • 丰富的 I/O 扩展接口 集成多套高速扩展接口，灵活应对各类计算机扩展需求：8 lanes PCIe、3 套 USB 3.0、1 套 GMAC 等。

  • 完整的硬件虚拟化

    完整的硬件虚拟化技术，支持 RV Hypervisor 1.0 扩展、RV AIA 扩展、RV IOMMU 扩展，提供 CPU、内存、中断、I/O 的完整硬件虚拟化。

  • 更高等级的安全防御技术 支持 M/S/U 三种处理器权限；支持硬件抵抗幽灵、熔断等攻击；支持国密 2、3、4 硬件安全技术。

  • 符合工业级标准 CPU 核、多级 Cache、SRAM 支持 ECC 设计，在 -40˚C～85˚C 的环境温度下仍能提供稳定可靠的持续算力输出，满足工业应用的苛刻环境需求。

1.3 应用​

  • AI 边缘计算
  • 大模型推理一体机
  • 智能机器人
  • 产品框图

1.4 订货型号​

下图展示了订货型号的命名规则，该规则由以下几个部分组成。

下表提供了具体的订货型号（Part Number）、主控型号以及对应的 DDR 容量信息。

订货型号主控型号DDR 容量
COM3K308128K38GB
COM3K316128K316GB
COM3K332128K332GB

2. 模块框图​

K3-CoM260 模块框图如下图所示。

注：有关各模块的详细技术参数，请参考相应的 K3 数据手册（Datasheet）。

2.1 接口定义​

下表列出了 K3-CoM260 的主要接口及其相关特性。

MIPI_DSI​

信号名称类型描述
MIPI_DSI1_LANEx_DP[1:0]ODSI1 DATA LANE ±
MIPI_DSI1_LANEx_DNx[1:0]ODSI1 DATA LANE ±
MIPI_DSI1_CLKPODSI1 Clock LANE ±
MIPI_DSI1_CLKNODSI1 Clock LANE ±

MIPI_CSI​

信号名称类型描述
MIPI_CSI0_DPx[1:0]ICSI0 DATA LANE ±
MIPI_CSI0_DNx[1:0]ICSI0 DATA LANE ±
MIPI_CSI1_DPx[3:0]ICSI1 DATA LANE ±
MIPI_CSI1_DNx[3:0]ICSI1 DATA LANE ±
MIPI_CSI2_DPx[1:0]ICSI2 DATA LANE ±
MIPI_CSI2_DNx[1:0]ICSI2 DATA LANE ±
MIPI_CSI3_DxP[1:0]ICSI3 DATA LANE ±
MIPI_CSI3_DxN[1:0]ICSI3 DATA LANE ±
MIPI_CSIx_CLKN[3:0]OCSI Clock LANE ±
MIPI_CSIx_CLKP[3:0]OCSI Clock LANE ±

DP 1.2​

信号名称类型描述
EDP1_TXxN[3:0]OEDP1 DATA LANE ±
EDP1_TXxP[3:0]O
DP1_AUXNOEDP1 Auxiliary LANE ±
DP1_AUXPO

eMMC​

信号名称类型描述
EMMC_Dx[7:0]I/OeMMC DATA
EMMC_CLKI/OeMMC Clock
EMMC_CMDI/OeMMC command
EMMC_DSI/OeMMC data strobe

SDIO 3.0​

信号名称类型描述
MMC1_DATx[3:0]I/OSD Card DATA
MMC1_CLKI/OSD Card Clock
MMC1_CMDI/OSD Card Command
MMC2_DATx[3:0]I/OSDIO DATA
MMC2_CLKI/OSDIO Clock
MMC2_CMDI/OSDIO Command

eSPI I/O​

信号名称类型描述
ESPI0_Dx[3:0]I/OFour data lines for command, address, and data transfer.
Operates in single-, dual-, or quad-I/O modes depending on configuration.
ESPI0_CS0IChip Select, active low.
Used by the master to select a specific slave device.
ESPI0_CLKIeSPI clock signal generated by the master.
Synchronizes data transfer between master and slave.

SPI​

信号名称类型描述
SPix[2:0]_SCLKI/OSynchronous Serial Port Clock 0/2
The serial bit clock can be configured as an output (master mode operation) or an input (slave mode operation).
SPix[2:0]_FRMI/OSynchronous Serial Port Frame 0/2
The serial frame sync can be configured as an output (master mode operation) or an input (slave mode operation).
SPix[2:0]_TXDOSynchronous Serial Port Transmit Data 0/2
Serial data driven out synchronously with the bit clock.
SPix[2:0]_RXDISynchronous Serial Port Receive Data 0/2
Serial data latched using the bit clock.
R.SPI0_SCLKI/ORT24 Synchronous Serial Port Clock 0/2
The serial bit clock can be configured as an output (master mode operation) or an input (slave mode operation).
R.SPI0_FRMI/ORT24 Synchronous Serial Port Frame 0/2
The serial frame sync can be configured as an output (master mode operation) or an input (slave mode operation).
R.SPI0_TXDORT24 Synchronous Serial Port Transmit Data 0/2
Serial data driven out synchronously with the bit clock.
R.SPI0_RXDIRT24 Synchronous Serial Port Receive Data 0/2
Serial data latched using the bit clock.

I2S​

信号名称类型描述
I2S0_SCLKI/OI2S Continues Serial Clock
I2S0_LRCKI/OI2S Left–Right Clock
I2S0_TXDOI2S Serial Transmit Data
I2S0_RXDII2S Serial Receive Data
I2Sx[5:2]_SCLKI/OI2S Continues Serial Clock
I2Sx[5:2]_LRCKI/OI2S Left–Right Clock
I2Sx[5:2]_TXDOI2S Serial Transmit Data
I2Sx[5:2]_RXDII2S Serial Receive Data

I2C​

信号名称类型描述
I2Cx[6:0]_SDAI/OI2C Serial Data
I2Cx[6:0]_SCLI/OI2C Serial Clock
R.I2Cx[1:0]_SDAI/ORT24 domain I2C Serial Data
R.I2Cx[1:0]_SCLI/ORT24 domain I2C Serial Clock

CAN-FD​

信号名称类型描述
CANx[4:0]_TXOCAN Transmit Data
CANx[4:0]_RXICAN Receive Data
R.CAN0_TXORT24 domain CAN Transmit Data
R.CAN0_RXIRT24 domain CAN Receive Data
R.CAN2_TXORT24 domain CAN Transmit Data
R.CAN2_RXIRT24 domain CAN Receive Data

FAN​

信号名称类型描述
PWMOFAN Pulse-width modulation
TACHIFAN Tachometer

UART​

信号名称类型描述
UART0_TXDODEBUG UART Transmit Data
UART0_RXDIDEBUG UART Receive Data
UART1_TXDOUART1 Transmit Data
UART1_RXDIUART1 Receive Data
UART1_CTS_NIUART1 Clear-to-Send
UART1_RTS_NOUART1 Request-to-Send
UARTx[10:3]_TXDOUART Transmit Data
UARTx[10:3]_RXDIUART Receive Data
UARTx[10:3]_CTS_NIUART Clear-to-Send
UARTx[10:3]_RTS_NOUART Request-to-Send
R.UART0_TXDORT24 domain UART Transmit Data
R.UART0_RXDIRT24 domain UART Receive Data
R.UARTx[5:2]_TXDORT24 domain UART Transmit Data
R.UARTx[5:2]_RXDIRT24 domain UART Receive Data

GPIO​

信号名称类型描述
GPIO[1]/[4]I/O3.3V GPIO domain
GPIO[2]/[3]/[5]I/O1.8V GPIO domain

USB 2.0​

信号名称类型描述
USB20_A_DRD_USB_MI/ODOWNLOAD USB D±, usually for USB 2.0
USB20_A_DRD_USB_PI/O

USB 3.0​

信号名称类型描述
USB20_A_DRD_USB_MI/ODOWNLOAD USB D±, usually for Download
USB20_A_DRD_USB_PI/O
USB_DRD_RXxN[1:0]I/OUSB 3.0 Receive Data ± for Download
USB_DRD_RXxP[1:0]I/O
USB_DRD_TXxN[1:0]I/OUSB 3.0 Transmit Data ± for Download
USB_DRD_TXxP[1:0]I/O

PCIe 3.0​

信号名称类型描述
PCIE_RXxN[1:0]I/OPCIe Receive Data ±, usually for PCIeB, PCIeC
PCIE_RXxP[1:0]I/O
PCIE_TXxN[1:0]I/OPCIe Transmit Data ±, usually for PCIeB, PCIeC
PCIE_TXxP[1:0]I/O
PCIE_REFCLK_NI/OPCIe Clock LANE ±, usually for PCIeA, PCIeB, PCIeC
PCIE_REFCLK_PI/O

GMAC​

信号名称类型描述
GMAC1_RXDVIGMAC1 Receive Data Valid
GMAC1_RX_Dx[3:0]IGMAC1 Receive Data
GMAC1_RX_CLKIGMAC1 Receive Clock
GMAC1_TX_Dx[3:0]OGMAC1 Transmit Data
GMAC1_TX_ENOGMAC1 Transmit Data Enable
GMAC1_MDCI/OGMAC1 Configuration interface clock
GMAC1_MDIOI/OGMAC1 Configuration interface I/O
GMAC1_INT_NI/OGMAC1 Interrupt

3. 引脚定义​

3.1 引脚实物​

下图展示了 K3-CoM260 模块的实物图。

3.2 引脚封装​

本节详细介绍了 K3-CoM260 的引脚封装信息。

K3-CoM260 模块采用以下封装规格：

  • 接口：金手指（260 Pin，SODIMM）
  • 尺寸：69.6 mm × 45.0 mm × 1.2 mm
  • 引脚间距（Pitch）：0.5 mm

下表提供了 K3-CoM260 的引脚布局。

Pin namePin No.Pin No.Pin Name
GND12GND
MIPI_CSI0_DN034MIPI_CSI1_DN0
MIPI_CSI0_DP056MIPI_CSI1_DP0
GND78GND
MIPI_CSI0_CLKN910MIPI_CSI1_CLKN
MIPI_CSI0_CLKP1112MIPI_CSI1_CLKP
GND1314GND
MIPI_CSI0_DN11516MIPI_CSI1_DN1
MIPI_CSI0_DP11718MIPI_CSI1_DP1
GND1920GND
MIPI_CSI2_DN22122MIPI_CSI2_DN0
MIPI_CSI2_DP22324MIPI_CSI2_DP0
GND2526GND
MIPI_CSI3_CLKN2728MIPI_CSI2_CLKN
MIPI_CSI3_CLKP2930MIPI_CSI2_CLKP
GND3132GND
MIPI_CSI2_DN33334MIPI_CSI2_DN1
MIPI_CSI2_DP33536MIPI_CSI2_DP1
GND3738GND
USB_DRD_RX1N3940PCIE4/USB3-D_RX0N
USB_DRD_RX1P4142PCIE4/USB3-D_RX0P
GND4344GND
USB_DRD_TX1N4546PCIE4/USB3-D_TX0N
USB_DRD_TX1P4748PCIE4/USB3-D_TX0P
GND4950GND
USB_DRD_RX2N5152PCIE4_REFCLK_N
USB_DRD_RX2P5354PCIE4_REFCLK_P
GND5556GND
USB_DRD_TX2N5758PCIE3/USB3-C_RX0N
USB_DRD_TX2P5960PCIE3/USB3-C_RX0P
GND6162GND
EDP1_TX0N6364PCIE3/USB3-C_TX0N
EDP1_TX0P6566PCIE3/USB3-C_TX0P
GND6768GND
EDP1_TX1N6970MIPI_DSI1_D0N
EDP1_TX1P7172MIPI_DSI1_D0P
GND7374GND
EDP1_TX2N7576MIPI_DSI1_CLKN
EDP1_TX2P7778MIPI_DSI1_CLKP
GND7980GND
EDP1_TX3N8182MIPI_DSI1_D1N
EDP1_TX3P8384MIPI_DSI1_D1P
GND8586GND
GPIO[3]_58 { GMAC2_PPS / R.UART2_RXD / R.CAN0_TXD / PCIEC_PERSTN / R.I2C0_SDA / PWM16 }8788GPIO[3]_74 { R.GMAC3_CLK_REF / CLK_CAMCK2 / ESPI0_RESETN / VCXO_REQ / USB30H-1_DRV / R.I2C0_SCL }
GPIO[5]_104 { SSP0_TXD / SSP2_TXD / USB30H-1_DRV / CAN3_RXD / PCIED_PWRDET }8990GPIO[3]_67 { R.GMAC3_TX_CLK / R.GPIO[22] / R.SSP1_FRM / CLK_CAMCK4 / PCIEC_PWRDET / R.PWM3 }
GPIO[5]_106 { SSP0_SCLK / SSP2_SCLK / R.I2C1_SDA / I2C3_SDA / PCIED_WAKEN / PWM18 }9192GPIO[3]_53 { GMAC2_TX_EN / UART3_CTSN / SSP0_TXD / PCIEA_EINT / PWM11 }
GPIO[5]_105 { SSP0_RXD / SSP2_RXD / R.I2C1_SCL / I2C3_SCL / PCIED_PERSTN / PWM17 }9394GPIO[1]_02 { GMAC0_RX_D1 / SSPA5_TXD / PWM2 / ESPI0_D2 / I2C1_SCL }
GPIO[5]_107 { SSP0_FRM / SSP2_FRM / R.CAN4_TXD / USB30-0_DIR / PCIED_CLKREQN / PWM19 }9596GPIO[3]_72 { R.GMAC3_MDIO / SSPA4_RXD / ESPI0_CS / E/DP1_HPD / DSI0_TE }
GPIO[3]_70 { R.GMAC3_TX_EN / SSPA4_FRM / ESPI0_D2 / IR1_RX / MNCLK_OUT1 / SSP3_SCLK }9798EDP1_AUXN
GPIO[3]_48 { GMAC2_TX_D0 / UART6_TXD / CAN1_RXD / PCIEA_AUXEN / I2C0_SCL / PWM6 }99100EDP1_AUXP
GPIO[3]_49 { GMAC2_TX_D1 / UART6_RXD / CAN1_TXD / PCIEA_PWRDET / I2C0_SDA / PWM7 }101102GND
GPIO[3]_51 { GMAC2_TX_D2 / UART6_RTS / CAN2_RXD / PCIEA_ATNLED / I2C4_SDA / PWM9 }103104GPIO[3]_60 { R.GMAC3_RX_D0 / R.UART5_RXD / R.SSP0_TXD / PCIEC_CLKREQN / R.I2C1_SDA / PWM18 }
GPIO[3]_50 { GMAC2_TX_CLK / UART6_CTS / CAN2_TXD / PCIEA_MRLN / I2C4_SCL / PWM8 }105106GPIO[3]_62 { R.GMAC3_RX_CLK / R.SSP0_SCLK / PCIEC_ATTN / I2C6_SDA }
GND107108GPIO[3]_61 { R.GMAC3_RX_D1 / R.SSP0_RXD / PCIEC_PRSNT2N / I2C6_SCL / PWM19 }
USB20_A_DRD_USB_M109110GPIO[3]_63 { R.GMAC3_RX_D2 / R.GPIO[18] / R.SSP0_FRM / PCIEC_PWRCTN / I2C5_SCL }
USB20_A_DRD_USB_P111112GPIO[3]_71 { R.GMAC3_MDC / SSPA4_TXD / ESPI0_D3 / R.IR0_RX / MNCLK_OUT2 / SSP3_FRM }
GND113114GPIO[3]_45 { GMAC2_RX_CLK / UART10_RXD / CAN0_RXD / PCIEA_PRSNT2N / PWM3 }
USB20_B_USB_M115116GPIO[3]_75 { R.GMAC3_PPS / CLK_CAMCK1 / ESPI0_ALERT / VCXO_OUT / USB30H-2_DRV / R.I2C0_SDA }
USB20_B_USB_P117118GPIO[5]_122 { MMC2_DAT[3] / SSPA1_CLK / UART6_TXD / R.UART0_TXD / PCIEB_ATNLED }
GND119120GPIO[3]_44 { GMAC2_RX_D1 / UART10_TXD / CAN0_TXD / PCIEA_CLKREQN / PWM2 }
USB20_HOST_M121122GPIO[4]_85 { CLK_CAMCK3 / SSPA0_SYSCLK / UART9_RXD / USB30-2_DRV / PCIEA_AUXEN }
USB20_HOST_P123124GPIO[4]_77 { R.SSPA0_FRM / SSPA2_FRM / UART8_RXD / CAN0_RXD / PCIEE_WAKEN / I2C0_SDA }
GND125126GPIO[3]_57 { GMAC2_CLK_REF / R.UART2_TXD / R.CAN0_RXD / EDP0_HPD / R.I2C0_SCL / PWM15 }
GPIO[3]_59 { R.GMAC3_RXDV / R.UART5_TXD / PCIEC_WAKEN / R.I2C1_SCL / PWM17 }127128GPIO[3]_73 { R.GMAC3_INT_N / SSPA4_SYSCLK / ESPI0_CLK / R.IR1_RX / USB20_HOST_DRV }
GND129130GPIO[5]_103 { / SSPA3_SYSCLK / USB20_HOST_DRV / CAN3_TXD / PCIED_AUXEN / I2C1_SDA }
PCIE0_RX0N131132GND
PCIE0_RX0P133134PCIE0_TX0N
GND135136PCIE0_TX0P
PCIE0_RX1N137138GND
PCIE0_RX1P139140PCIE0_TX1N
GND141142PCIE0_TX1P
GPIO[4]_87 { R.SSP0_RXD / R.ESPI0_D1 / UART4_RXD / CAN2_RXD / PCIEA_MRLN / PCIEB_PRSNT2N }143144GND
GPIO[4]_86 { R.SSP0_TXD / R.ESPI0_D0 / UART4_TXD / CAN2_TXD / PCIEA_PWRDET / USB30-0_DIR }145146GND
GND147148PCIE1_TX0N
PCIE1_RX0N149150PCIE1_TX0P
PCIE1_RX0P151152GND
GND153154PCIE1_TX1N
PCIE1_RX1N155156PCIE1_TX1P
PCIE1_RX1P157158GND
GND159160PCIE0_REFCLK_N
PCIE2/USB3-B_RX0N161162PCIE0_REFCLK_P
PCIE2/USB3-B_RX0P163164GND
GND165166PCIE2/USB3-B_TX0N
PCIE5_RX0N167168PCIE2/USB3-B_TX0P
PCIE5_RX0P169170GND
GND171172PCIE5_TX0N
PCIE5_REFCLK_N173174PCIE5_TX0P
PCIE5_REFCLK_P175176GND
GND177178GPIO[3]_42 { GMAC2_RXDV / UART0_TXD / PCIEA_PERSTN / I2C0_SCL / PWM0 }
GPIO[4]_80 { R.SSPA0_SYSCLK / SSPA2_SYSCLK / R.UART4_TXD / CAN3_RXD / PCIEA_WAKEN / I2C2_SCL }179180GPIO[4]_81 { SSP0_TXD / SSPA0_CLK / R.UART4_RXD / CAN3_TXD / PCIEA_CLKREQN / I2C2_SDA }
GPIO[4]_79 { R.SSPA0_RXD / SSPA2_RXD / UART8_RTS / PCIEA_PERSTN / I2C1_SDA }181182GPIO[4]_78 { R.SSPA0_TXD / SSPA2_TXD / UART8_CTS / PCIEE_CLKREQN / I2C1_SCL }
GPIO[4]_76 { R.SSPA0_CLK / SSPA2_CLK / UART8_TXD / CAN0_TXD / PCIEE_PERSTN / I2C0_SCL }183184PHY1_MDI0-
GPIO[1]_00 { GMAC0_RXDV / SSPA5_CLK / PWM0 / IR1_RX / ESPI0_D0 / I2C0_SCL }185186PHY1_MDI0+
GPIO[1]_01 { GMAC0_RX_D0 / SSPA5_FRM / PWM1 / R.IR1_RX / ESPI0_D1 / I2C0_SDA }187188PHY1_LED1/CFG_LDO0
GPIO[4]_82 { SSP0_TXD / SSPA0_FRM / UART9_CTSN / UART5_RXD / PCIEA_PRSNT2N / I2C3_SCL }189190PHY1_MDI1-
GPIO[4]_83 { SSP0_SCLK / SSPA0_TXD / UART9_RTSN / UART5_TXD / PCIEA_ATTN / I2C3_SDA }191192PHY1_MDI1+
GPIO[5]_113 { SSP1_SCLK / SSPA0_TXD / R.GPIO[30] / PCIEB_PERSTN / }193194PHY1_LED2/CFG_LDO1
GPIO[5]_114 { SSP1_FRM / SSPA0_RXD / R.GPIO[31] / PCIEB_WAKEN / }195196PHY1_MDI2-
GPIO[5]_112 { SSP1_RXD / SSPA0_FRM / UCIE_DESDA / I2C4_SDA / USB30-3_DRV / R.PWM9 }197198PHY1_MDI2+
GPIO[5]_111 { SSP1_TXD / SSPA0_CLK / UCIE_DESCL / I2C4_SCL / USB30-0_INT / R.PWM8 }199200GND
GND201202PHY1_MDI3-
GPIO[5]_121 { UART1_TXD / I2C2_SDA / R.CAN3_RXD / CAN4_RXD / PCIEB_MRLN }203204PHY1_MDI3+
GPIO[5]_120 { UART1_RXD / I2C2_SCL / R.CAN3_TXD / CAN4_TXD / PCIEB_PWRDET }205206GPIO[5]_123 { MMC2_DAT[2] / SSPA1_FRM / UART6_RXD / R.UART0_RXD / PCIEB_PWRLED / }
GPIO[5]_118 { UART1_RTSN / USB30_DRD_DRV / R.GPIO[35] / PCIEB_PWRCTN }207208FAN_TACH(1V8)
GPIO[5]_119 { UART1_CTSN / USB30-0_INT / PCIEB_AUXEN }209210PMIC_32K_OUT(3V3)
GPIO[5]_124 { MMC2_DAT[1] / SSPA1_TXD / PCIED_PERSTN / E/DP0_HPD / PCIEB_EINT / }211212GPIO[3]_56 { GMAC2_INT_N / UART3_TXD / SSP0_FRM / R.UART3_TXD / PWM14 }
GPIO[4]_93 { R.GPIO[25] / R.ESPI0_ALERT / UART0_TXD / ESPI0_D2 / I2C5_SCL / R.PWM4 }213214GPIO[3]_69 { R.GMAC3_TX_D3 / SSPA4_CLK / ESPI0_D1 / E/DP1_HPD / DSI0_TE / SSP3_RXD }
GPIO[4]_94 { R.GPIO[26] / UART0_RXD / ESPI0_D3 / I2C5_SDA / R.PWM6 }215216GPIO[5]_125 { MMC2_DAT[0] / SSPA1_RXD / PCIED_WAKEN / E/DP1_HPD / PCIEB_EINTEG }
NA217218GPIO[5]_126 { MMC2_CMD / SSPA1_SYSCLK / PCIED_CLKREQN / I2C5_SCL / }
GPIO[1]_03 { GMAC0_RX_CLK / SSPA5_RXD / PWM3 / PCIED_PERSTN / ESPI0_D3 / I2C1_SDA }219220GPIO[5]_101 { SSP3_SCLK / SSPA3_TXD / UART4_CTS / CAN4_RXD / PCIED_ATTN / MNCLK_OUT1 }
GPIO[1]_05 { GMAC0_RX_D3 / PWM5 / PCIED_CLKREQN / ESPI0_CLK / I2C2_SCL }221222GPIO[5]_102 { SSP3_FRM / SSPA3_RXD / UART4_RTS / CAN4_TXD / PCIED_PWRCTN / I2C1_SCL }
GPIO[1]_12 { GMAC0_MDC / UART7_CTSN / CAN0_RXD / PCIEC_PERSTN / UART8_TXD / I2C4_SDA }223224GPIO[5]_100 { SSP3_RXD / SSPA3_FRM / UART4_RXD / R.CAN2_RXD / PCIED_PRSNT2N / CLK32K_OUT }
GPIO[1]_14 { GMAC0_INT_N / UART7_RXD / PWM14 / PCIEC_CLKREQN / MNCLK_OUT1 / I2C6_SCL }225226GPIO[5]_99 { SSP3_TXD / SSPA3_CLK / UART4_TXD / R.CAN2_TXD / CLK_CAMCK4 }
PCIE3_REFCLK_N227228GPIO[5]_127 { MMC2_CLK / PCIED_PRSNT2N / I2C5_SDA / USB30-2_DRV }
PCIE3_REFCLK_P229230FAN_PWM(1V8)
GND231232GPIO[3]_54 { GMAC2_MDC / UART3_RTSN / SSP0_RXD / PCIEA_EINTEG / I2C1_SCL / PWM12 }
GPIO[4]_88 { R.SSP0_SCLK / R.ESPI0_D2 / R.UART3_TXD / PCIEB_PERSTN / PCIEA_ATNLED / CAN1_RXD }233234GPIO[3]_55 { GMAC2_MDIO / UART3_RXD / SSP0_SCLK / R.UART3_RXD / I2C1_SDA / PWM13 }
VCC_RTC(5V)235236PWR_SSP_SCLK { GPIO[122] / UART0_TXD }
POWER_EN(5V)237238PWR_SSP_FRM { GPIO[123] / UART0_RXD }
PMIC_RST_OUTn(1V8)239240GPIO[4]_84 { SSP0_FRM / SSPA0_RXD / UART9_TXD / USB30-1_DRV / PCIEA_PWRCTN / DSI0_TE }
GND241242GND
GND243244GND
GND245246GND
GND247248GND
GND249250GND
VDD_IN(5V/20V)251252VDD_IN(5V/20V)
VDD_IN(5V/20V)253254VDD_IN(5V/20V)
VDD_IN(5V/20V)255256VDD_IN(5V/20V)
VDD_IN(5V/20V)257258VDD_IN(5V/20V)
VDD_IN(5V/20V)259260VDD_IN(5V/20V)

下表列出了 K3-CoM260 的引脚类型定义。

PINPin definitionPin NO.Pad TypeIO power domainFunction for K3-CoM260_KITDefault function description
1GNDGGNDDigital core Ground
3MIPI_CSI0_DN0AG39IMIPI_CSI0_DN0CSI0 DATA0 LANEN
5MIPI_CSI0_DP0AG38IMIPI_CSI0_DP0CSI0 DATA0 LANEP
7GNDGGNDDigital core Ground
9MIPI_CSI0_CLKNAF36OMIPI_CSI0_CLKNCSI0 Clock LANEN
11MIPI_CSI0_CLKPAF37OMIPI_CSI0_CLKPCSI0 Clock LANEP
13GNDGGNDDigital core Ground
15MIPI_CSI0_DN1AF40IMIPI_CSI0_DN1CSI0 DATA1 LANEN
17MIPI_CSI0_DP1AF39IMIPI_CSI0_DP1CSI0 DATA1 LANEP
19GNDGGNDDigital core Ground
21MIPI_CSI2_DN2V39IMIPI_CSI2_DN2CSI2 DATA2 LANEN
23MIPI_CSI2_DP2V40IMIPI_CSI2_DP2CSI2 DATA2 LANEP
25GNDGGNDDigital core Ground
27MIPI_CSI3_CLKNW38OMIPI_CSI3_CLKNCSI3 Clock LANEN
29MIPI_CSI3_CLKPW39OMIPI_CSI3_CLKPCSI3 Clock LANEP
31GNDGGNDDigital core Ground
33MIPI_CSI2_DN3V36IMIPI_CSI2_DN3CSI2 DATA3 LANEN
35MIPI_CSI2_DP3V37IMIPI_CSI2_DP3CSI2 DATA3 LANEP
37GNDGGNDDigital core Ground
39USB_DRD_RX1NAT12IUSB_DRD_RX1NUSB3.0_DRD RX1 LANEN
41USB_DRD_RX1PAU12IUSB_DRD_RX1PUSB3.0_DRD RX1 LANEP
43GNDGGNDDigital core Ground
45USB_DRD_TX1NAY10OUSB_DRD_TX1NUSB3.0_DRD TX1 LANEN
47USB_DRD_TX1PAW10OUSB_DRD_TX1PUSB3.0_DRD TX1 LANEP
49GNDGGNDDigital core Ground
51USB_DRD_RX2NAW11IUSB_DRD_RX2NUSB3.0_DRD RX2 LANEN
53USB_DRD_RX2PAV11IUSB_DRD_RX2PUSB3.0_DRD RX2 LANEP
55GNDGGNDDigital core Ground
57USB_DRD_TX2NAW12OUSB_DRD_TX2NUSB3.0_DRD TX2 LANEN
59USB_DRD_TX2PAY12OUSB_DRD_TX2PUSB3.0_DRD TX2 LANEP
61GNDGGNDDigital core Ground
63EDP1_TX0NAT18ODP1_TX0NDP DATA0 LANEN
65EDP1_TX0PAU18ODP1_TX0PDP DATA0 LANEP
67GNDGGNDDigital core Ground
69EDP1_TX1NAW18ODP1_TX1NDP DATA1 LANEN
71EDP1_TX1PAY18ODP1_TX1PDP DATA1 LANEP
73GNDGGNDDigital core Ground
75EDP1_TX2NAW19ODP1_TX2NDP DATA2 LANEN
77EDP1_TX2PAV19ODP1_TX2PDP DATA2 LANEP
79GNDGGNDDigital core Ground
81EDP1_TX3NAW20ODP1_TX3NDP DATA3 LANEN
83EDP1_TX3PAY20ODP1_TX3PDP DATA3 LANEP
85GNDGGNDDigital core Ground
87GPIO[3]_58 {GMAC2_PPS/R.UART2_RXD/R.CAN0_TXD/PCIEC_PERSTN/R.I2C0_SDA/PWM16 }M36I1.8VUSB0_VBUS_DETGeneral purpose I/O3 58
89GPIO[5]_104 { SSP0_TXD / SSP2_TXD / USB30H-1_DRV / CAN3_RXD / PCIED_PWRDET / }AW27O1.8VSPI0_MOSISPI0_MOSI
91GPIO[5]_106 { SSP0_SCLK / SSP2_SCLK / R.I2C1_SDA / I2C3_SDA / PCIED_WAKEN / PWM18 }AP27O1.8VSPI0_SCKSPI0_SCK
93GPIO[5]_105 { SSP0_RXD / SSP2_RXD / R.I2C1_SCL / I2C3_SCL / PCIED_PERSTN / PWM17 }AR27I1.8VSPI0_MISOSPI0_MISO
95GPIO[5]_107 { SSP0_FRM / SSP2_FRM / R.CAN4_TXD / USB30-0_DIR / PCIED_CLKREQN / PWM19 }AY27I1.8VSPI0_CSSPI0_CS
97GPIO[3]_70 { R.GMAC3_TX_EN / SSPA4_FRM / ESPI0_D2 / IR1_RX / MNCLK_OUT1 / SSP3_SCLK }J40I1.8VSPI0_CS1General purpose I/O3 70
99GPIO[3]_48 { GMAC2_TX_D0 / UART6_TXD / CAN1_RXD / PCIEA_AUXEN / I2C0_SCL / PWM6 }J35O1.8VUART6_TXDUART6_TXD
101GPIO[3]_49 { GMAC2_TX_D1 / UART6_RXD / CAN1_TXD / PCIEA_PWRDET / I2C0_SDA / PWM7 }K35I1.8VUART6_RXDUART6_RXD
103GPIO[3]_51 { GMAC2_TX_D2 / UART6_RTS / CAN2_RXD / PCIEA_ATNLED / I2C4_SDA / PWM9 }M35I1.8VUART6_RTSUART6_RTS
105GPIO[3]_50 { GMAC2_TX_CLK / UART6_CTS / CAN2_TXD / PCIEA_MRLN / I2C4_SCL / PWM8 }L35O1.8VUART6_CTSUART6_RTS
107GNDGGNDDigital core Ground
109USB20_A_DRD_USB_MAU14I/OUSB20_A_DRD_USB_MUSB2.0_A_DRD D- differential data line
111USB20_A_DRD_USB_PAT14I/OUSB20_A_DRD_USB_PUSB2.0_A_DRD D+ differential data line
113GNDGGNDDigital core Ground
115USB20_B_USB_MC18I/OUSB20_B_USB_MUSB2.0_B D- differential data line
117USB20_B_USB_PB18I/OUSB20_B_USB_PUSB2.0_B D+ differential data line
119GNDGGNDDigital core Ground
121USB20_HOST_MB22I/OUSB20_HOST_MUSB2.0_HOST D- differential data line
123USB20_HOST_PC22I/OUSB20_HOST_PUSB2.0_HOST D+ differential data line
125GNDGGNDDigital core Ground
127GPIO[3]_59 { R.GMAC3_RXDV / R.UART5_TXD / PCIEC_WAKEN / R.I2C1_SCL / PWM17 }J38O1.8VPWR_LED_CTRLGeneral purpose I/O3 59
129GNDGGNDDigital core Ground
131PCIE0_RX0NG22IPCIE0_RX0NPCIE0 RX0 LANEN
133PCIE0_RX0PF22IPCIE0_RX0PPCIE0 RX0 LANEP
135GNDGGNDDigital core Ground
137PCIE0_RX1NE21IPCIE0_RX1NPCIE0 RX1 LANEN
139PCIE0_RX1PD21IPCIE0_RX1PPCIE0 RX1 LANEP
141GNDGGNDDigital core Ground
143GPIO[4]_87 { R.SSP0_RXD / R.ESPI0_D1 / UART4_RXD / CAN2_RXD / PCIEA_MRLN / PCIEB_PRSNT2N }AU35I3.3VCAN2_RXDCAN2_RXD
145GPIO[4]_86 { R.SSP0_TXD / R.ESPI0_D0 / UART4_TXD / CAN2_TXD / PCIEA_PWRDET / USB30-0_DIR }AT35O3.3VCAN2_TXDCAN2_TXD
147GNDGGNDDigital core Ground
149PCIE1_RX0NE19IPCIE1_RX0NPCIE1 RX0 LANEN
151PCIE1_RX0PD19IPCIE1_RX0PPCIE1 RX0 LANEP
153GNDGGNDDigital core Ground
155PCIE1_RX1NF18IPCIE1_RX1NPCIE1 RX1 LANEN
157PCIE1_RX1PG18IPCIE1_RX1PPCIE1 RX1 LANEP
159GNDGGNDDigital core Ground
161PCIE2/USB3-B_RX0NE17IPCIE2/USB3-B_RX0NUSB3.0_B RX0 LANEN
163PCIE2/USB3-B_RX0PD17IPCIE2/USB3-B_RX0PUSB3.0_B RX0 LANEP
165GNDGGNDDigital core Ground
167PCIE5_RX0NE9IPCIE5_RX0NPCIE5 RX0 LANEN
169PCIE5_RX0PD9IPCIE5_RX0PPCIE5 RX0 LANEP
171GNDGGNDDigital core Ground
173PCIE5_REFCLK_NB8OPCIE5_REFCLK_NPCIE5 Clock LANEN
175PCIE5_REFCLK_PC8OPCIE5_REFCLK_PPCIE5 Clock LANEP
177GNDGGNDDigital core Ground
179GPIO[4]_80 { R.SSPA0_SYSCLK / SSPA2_SYSCLK / R.UART4_TXD / CAN3_RXD / PCIEA_WAKEN / I2C2_SCL }AR34I3.3VPCIeA_WAKEnPCIeA_WAKEn
181GPIO[4]_79 { R.SSPA0_RXD / SSPA2_RXD / UART8_RTS / PCIEA_PERSTN / I2C1_SDA }AP34O3.3VPCIeA_PERSTnPCIeA_PERSTn
183GPIO[4]_76 { R.SSPA0_CLK / SSPA2_CLK / UART8_TXD / CAN0_TXD / PCIEE_PERSTN / I2C0_SCL }AR33O3.3VPCIeE_PERSTnPCIeA_PERSTn
185GPIO[1]_00 { GMAC0_RXDV / SSPA5_CLK / PWM0 / IR1_RX / ESPI0_D0 / I2C0_SCL }AY32O3.3VI2C0_SCLI2C0_SCL
187GPIO[1]_01 { GMAC0_RX_D0 / SSPA5_FRM / PWM1 / R.IR1_RX / ESPI0_D1 / I2C0_SDA }AW32I/O3.3VI2C0_SDAI2C0_SDA
189GPIO[4]_82 { SSP0_RXD / SSPA0_FRM / UART9_CTSN / UART5_RXD / PCIEA_PRSNT2N / I2C3_SCL }AV34O3.3VI2C3_SCLI2C3_SCL
191GPIO[4]_83 { SSP0_SCLK / SSPA0_TXD / UART9_RTSN / UART5_TXD / PCIEA_ATTN / I2C3_SDA }AW34I/O3.3VI2C3_SDAI2C3_SDA
193GPIO[5]_113 { SSP1_SCLK / SSPA0_TXD / R.GPIO[30] / PCIEB_PERSTN }AY26O1.8VI2S0_SDOUTI2S0_SDOUT
195GPIO[5]_114 { SSP1_FRM / SSPA0_RXD / R.GPIO[31] / PCIEB_WAKEN }AP25I1.8VI2S0_SDINI2S0_SDIN
197GPIO[5]_112 { SSP1_RXD / SSPA0_FRM / UCIE_DESDA / I2C4_SDA / USB30-3_DRV / R.PWM9 }AW26I1.8VI2S0_LRCKI2S0_LRCK
199GPIO[5]_111 { SSP1_TXD / SSPA0_CLK / UCIE_DESCL / I2C4_SCL / USB30-0_INT / R.PWM8 }AU26O1.8VI2S0_CLKI2S0_CLK
201GNDGGNDDigital core Ground
203GPIO[5]_121 { UART1_TXD / I2C2_SDA / R.CAN3_RXD / CAN4_RXD / PCIEB_MRLN }AT24O1.8VUART1_TXDUART1_TXD
205GPIO[5]_120 { UART1_RXD / I2C2_SCL / R.CAN3_TXD / CAN4_TXD / PCIEB_PWRDET / }AR24I1.8VUART1_RXDUART1_TXD
207GPIO[5]_118 { UART1_RTSN / USB30_DRD_DRV / R.GPIO[35] / PCIEB_PWRCTN }AW25I1.8VUART1_RTSnUART1_RTSn
209GPIO[5]_119 { UART1_CTSN / USB30-0_INT / PCIEB_AUXEN / }AP24O1.8VUART1_CTSnUART1_CTSn
211GPIO[5]_124 { MMC2_DAT[1] / SSPA1_TXD / PCIED_PERSTN / E/DP0_HPD / PCIEB_EINT }AT23I/O1.8VMMC2_DAT1General purpose I/O5 124
213GPIO[4]_93 { R.GPIO[25] / R.ESPI0_ALERT / UART0_TXD / ESPI0_D2 / I2C5_SCL / R.PWM4 }AW37O3.3VI2C5_SCLI2C5_SCL
215GPIO[4]_94 { R.GPIO[26] / UART0_RXD / ESPI0_D3 / I2C5_SDA / R.PWM6 }AY37I/O3.3VI2C5_SDAI2C5_SDA
217NAI/O3.3VMODULE_IDNA
219GPIO[1]_03 { GMAC0_RX_CLK / SSPA5_RXD / PWM3 / PCIED_PERSTN / ESPI0_D3 / I2C1_SDA }AU32O3.3VPCIeD_PERSTnPCIeD_PERSTn
221GPIO[1]_05 { GMAC0_RX_D3 / PWM5 / PCIED_CLKREQN / ESPI0_CLK / I2C2_SCL }AP32I3.3VPCIeD_CLKREQnPCIeD_CLKREQn
223GPIO[1]_12 { GMAC0_MDC / UART7_CTSN / CAN0_RXD / PCIEC_PERSTN / UART8_TXD / I2C4_SDA }AW30O3.3VPCIeC_PERSTnPCIeC_PERSTn
225GPIO[1]_14 { GMAC0_INT_N / UART7_RXD / PWM14 / PCIEC_CLKREQN / MNCLK_OUT1 / I2C6_SCL }AW29I3.3VPCIeC_CLKREQnPCIeC_CLKREQn
227PCIE3_REFCLK_NB12OPCIE3_REFCLK_NPCIE3 Clock LANEN
229PCIE3_REFCLK_PC12OPCIE3_REFCLK_PPCIE3 Clock LANEP
231GNDGGNDDigital core Ground
233GPIO[4]_88 { R.SSP0_SCLK / R.ESPI0_D2 / R.UART3_TXD / PCIEB_PERSTN / PCIEA_ATNLED / CAN1_RXD }AV35O3.3VSHUTDOWN_REQGeneral purpose I/O4 88
235VCC_RTC(5V)1.85-5.5VVCC_RTCRTC power
237POWER_EN(5V)I5VPOWER_ENK3-CoM260 Power Enable
239PMIC_RST_OUTn(1V8)O1.8VPMIC_RST_OUTnK3-CoM260 Reset
241GNDGGGNDDigital core Ground
243GND
245GND
247GND
249GND
251VDD_IN(5V/20V)P5V/9~19VVDD_INK3-CoM260 Power
253VDD_IN(5V/20V)
255VDD_IN(5V/20V)
257VDD_IN(5V/20V)
259VDD_IN(5V/20V)
2GNDGGNDDigital core Ground
4MIPI_CSI1_DN0AD37IMIPI_CSI1_DN0CSI1 DATA0 LANEN
6MIPI_CSI1_DP0AD36IMIPI_CSI1_DP0CSI1 DATA0 LANEP
8GNDGGNDDigital core Ground
10MIPI_CSI1_CLKNAB39OMIPI_CSI1_CLKNCSI1 Clock LANEN
12MIPI_CSI1_CLKPAB40OMIPI_CSI1_CLKPCSI1 Clock LANEP
14GNDGGNDDigital core Ground
16MIPI_CSI1_DN1AC39IMIPI_CSI1_DN1CSI1 DATA1 LANEN
18MIPI_CSI1_DP1AC38IMIPI_CSI1_DP1CSI1 DATA1 LANEP
20GNDGGNDDigital core Ground
22MIPI_CSI2_DN0Y40IMIPI_CSI2_DN0CSI2 DATA0 LANEN
24MIPI_CSI2_DP0Y39IMIPI_CSI2_DP0CSI2 DATA0 LANEP
26GNDGGNDDigital core Ground
28MIPI_CSI2_CLKNAB33OMIPI_CSI2_CLKNCSI2 Clock LANEN
30MIPI_CSI2_CLKPAB34OMIPI_CSI2_CLKPCSI2 Clock LANEP
32GNDGGNDDigital core Ground
34MIPI_CSI2_DN1Y37IMIPI_CSI2_DN1CSI2 DATA1 LANEN
36MIPI_CSI2_DP1Y36IMIPI_CSI2_DP1CSI2 DATA1 LANEP
38GNDGGNDDigital core Ground
40PCIE4/USB3-D_RX0ND13IPCIE4/USB3-D_RX0NPCIE4 RX0 LANEN
42PCIE4/USB3-D_RX0PE13IPCIE4/USB3-D_RX0PPCIE4 RX0 LANEP
44GNDGGNDDigital core Ground
46PCIE4/USB3-D_TX0NA9OPCIE4/USB3-D_TX0NPCIE4 TX0 LANEN
48PCIE4/USB3-D_TX0PB9OPCIE4/USB3-D_TX0PPCIE4 TX0 LANEP
50GNDGGNDDigital core Ground
52PCIE4_REFCLK_NC10OPCIE4_REFCLK_NPCIE4 Clock LANEN
54PCIE4_REFCLK_PB10OPCIE4_REFCLK_PPCIE4 Clock LANEP
56GNDGGNDDigital core Ground
58PCIE3/USB3-C_RX0ND15IPCIE3/USB3-C_RX0NPCIE3 RX0 LANEN
60PCIE3/USB3-C_RX0PE15IPCIE3/USB3-C_RX0PPCIE3 RX0 LANEP
62GNDGGNDDigital core Ground
64PCIE3/USB3-C_TX0NA11OPCIE3/USB3-C_TX0NPCIE3 TX0 LANEN
66PCIE3/USB3-C_TX0PB11OPCIE3/USB3-C_TX0PPCIE3 TX0 LANEP
68GNDGGNDDigital core Ground
70MIPI_DSI1_D0NAK34OMIPI_DSI1_D0NDSI 1 DATA0 LANEN
72MIPI_DSI1_D0PAK33OMIPI_DSI1_D0PDSI 1 DATA0 LANEP
74GNDGGNDDigital core Ground
76MIPI_DSI1_CLKNAJ38OMIPI_DSI1_CLKNDSI 1 Clock LANEN
78MIPI_DSI1_CLKPAJ39OMIPI_DSI1_CLKPDSI 1 Clock LANEP
80GNDGGNDDigital core Ground
82MIPI_DSI1_D1NAH39OMIPI_DSI1_D1NDSI 1 DATA1 LANEN
84MIPI_DSI1_D1PAH40OMIPI_DSI1_D1PDSI 1 DATA1 LANEP
86GNDGGNDDigital core Ground
88GPIO[3]_74 { R.GMAC3_CLK_REF / CLK_CAMCK2 / ESPI0_RESETN / VCXO_REQ / USB30H-1_DRV / R.I2C0_SCL }N40O1.8VCLK_CAMCK2CLK_CAMCK2
90GPIO[3]_67 { R.GMAC3_TX_CLK / R.GPIO[22] / R.SSP1_FRM / CLK_CAMCK4 / PCIEC_PWRDET / R.PWM3 }M39O1.8VCLK_CAMCK4CLK_CAMCK4
92GPIO[3]_53 { GMAC2_TX_EN / UART3_CTSN / SSP0_TXD / PCIEA_EINT / PWM11 }H36O1.8VMIPI_CSI3_PWDNGeneral purpose I/O3 53
94GPIO[1]_02 { GMAC0_RX_D1 / SSPA5_TXD / PWM2 / ESPI0_D2 / I2C1_SCL }AV32O1.8VMIPI_CSI1_PWDNGeneral purpose I/O1 02
96GPIO[3]_72 { R.GMAC3_MDIO / SSPA4_RXD / ESPI0_CS / E/DP1_HPD / DSI0_TE }L40I1.8Ve/DP1_HPDe/DP1_HPD
98EDP1_AUXNAW17I/ODP1_AUXNDP1 AUX LANEN
100EDP1_AUXPAV17I/ODP1_AUXPDP1 AUX LANEP
102GNDGGNDDigital core Ground
104GPIO[3]_60 { R.GMAC3_RX_D0 / R.UART5_RXD / R.SSP0_TXD / PCIEC_CLKREQN / R.I2C1_SDA / PWM18 }L38O1.8VR-SPI0_MOSIR.SPI0_MOSI
106GPIO[3]_62 { R.GMAC3_RX_CLK / R.SSP0_SCLK / PCIEC_ATTN / I2C6_SDA }N38O1.8VR-SPI0_SCKR.SPI0_SCK
108GPIO[3]_61 { R.GMAC3_RX_D1 / R.SSP0_RXD / PCIEC_PRSNT2N / I2C6_SCL / PWM19 }M38I1.8VR-SPI0_MISOR.SPI0_MISO
110GPIO[3]_63 { R.GMAC3_RX_D2 / R.GPIO[18] / R.SSP0_FRM / PCIEC_PWRCTN / I2C5_SCL }P38I1.8VR-SPI0_CSR.SPI0_CS
112GPIO[3]_71 { R.GMAC3_MDC / SSPA4_TXD / ESPI0_D3 / R.IR0_RX / MNCLK_OUT2 / SSP3_FRM }K40I1.8VR-SPI0_CS1General purpose I/O3 71
114GPIO[3]_45 { GMAC2_RX_CLK / UART10_RXD / CAN0_RXD / PCIEA_PRSNT2N / PWM3 }L34O1.8VMIPI_CSI0_PWDNGeneral purpose I/O3 45
116GPIO[3]_75 { R.GMAC3_PPS / CLK_CAMCK1 / ESPI0_ALERT / VCXO_OUT / USB30H-2_DRV / R.I2C0_SDA }P40O1.8VCLK_CAMCK1General purpose I/O3 75
118GPIO[5]_122 { MMC2_DAT[3] / SSPA1_CLK / UART6_TXD / R.UART0_TXD / PCIEB_ATNLED }AW24I/O1.8VMMC2_DAT3General purpose I/O5 122
120GPIO[3]_44 { GMAC2_RX_D1 / UART10_TXD / CAN0_TXD / PCIEA_CLKREQN / PWM2 }K34O1.8VMIPI_CSI2_PWDNGeneral purpose I/O3 44
122GPIO[4]_85 { CLK_CAMCK3 / SSPA0_SYSCLK / UART9_RXD / USB30-2_DRV / PCIEA_AUXEN }AY33O1.8VCLK_CAMCK3CLK_CAMCK3
124GPIO[4]_77 { R.SSPA0_FRM / SSPA2_FRM / UART8_RXD / CAN0_RXD / PCIEE_WAKEN / I2C0_SDA }AT33I3.3VBT_M2_WAKE_APGeneral purpose I/O4 77
126GPIO[3]_57 { GMAC2_CLK_REF / R.UART2_TXD / R.CAN0_RXD / EDP0_HPD / R.I2C0_SCL / PWM15 }L37O1.8VBT_M2_ENGeneral purpose I/O3 57
128GPIO[3]_73 { R.GMAC3_INT_N / SSPA4_SYSCLK / ESPI0_CLK / R.IR1_RX / USB20_HOST_DRV }M40O1.8VW_DISABLE1_CTRLGeneral purpose I/O3 73
130GPIO[5]_103 { SSPA3_SYSCLK / USB20_HOST_DRV / CAN3_TXD / PCIED_AUXEN / I2C1_SDA }AY28O1.8VCAM_MUX_SELGeneral purpose I/O5 103
132GNDGGNDDigital core Ground
134PCIE0_TX0NA21OPCIE0_TX0NPCIE0 TX0 LANEN
136PCIE0_TX0PB21OPCIE0_TX0PPCIE0 TX0 LANEP
138GNDGGNDDigital core Ground
140PCIE0_TX1NB19OPCIE0_TX1NPCIE0 TX1 LANEN
142PCIE0_TX1PA19OPCIE0_TX1PPCIE0 TX1 LANEP
144GNDGGNDDigital core Ground
146GNDGGNDDigital core Ground
148PCIE1_TX0NA17OPCIE1_TX0NPCIE1 TX0 LANEN
150PCIE1_TX0PB17OPCIE1_TX0PPCIE1 TX0 LANEP
152GNDGGNDDigital core Ground
154PCIE1_TX1NB15OPCIE1_TX1NPCIE1 TX1 LANEN
156PCIE1_TX1PA15OPCIE1_TX1PPCIE1 TX1 LANEP
158GNDGGNDDigital core Ground
160PCIE0_REFCLK_NC20OPCIE0_REFCLK_NPCIE0 Clock LANEN
162PCIE0_REFCLK_PB20OPCIE0_REFCLK_PPCIE0 Clock LANEP
164GNDGGNDDigital core Ground
166PCIE2/USB3-B_TX0NA13OPCIE2/USB3-B_TX0NUSB3_B TX0 LANEN
168PCIE2/USB3-B_TX0PB13OPCIE2/USB3-B_TX0PUSB3_B TX0 LANEP
170GNDGGNDDigital core Ground
172PCIE5_TX0NA7OPCIE5_TX0NPCIE5 TX0 LANEN
174PCIE5_TX0PB7OPCIE5_TX0PPCIE5 TX0 LANEP
176GNDGGNDDigital core Ground
178GPIO[3]_42 { GMAC2_RXDV / UART0_TXD / PCIEA_PERSTN / I2C0_SCL / PWM0 }H34O1.8VMOD_SLEEPGeneral purpose I/O3 42
180GPIO[4]_81 { SSP0_TXD / SSPA0_CLK / R.UART4_RXD / CAN3_TXD / PCIEA_CLKREQN / I2C2_SDA }AT34I3.3VPCIeA_CLKREQnPCIeA_CLKREQn
182GPIO[4]_78 { R.SSPA0_TXD / SSPA2_TXD / UART8_CTS / PCIEE_CLKREQN / I2C1_SCL }AP35I3.3VPCIeE_CLKREQnPCIeE_CLKREQn
184PHY1_MDI0-I/OPHY1_MDI0-PHY1 MDI0 LANEN
186PHY1_MDI0+I/OPHY1_MDI0+PHY1 MDI0 LANEP
188PHY1_LED1/CFG_LDO0OPHY1_LED1/CFG_LDO0PHY1_LED1/CFG_LDO0
190PHY1_MDI1-I/OPHY1_MDI1-PHY1 MDI1 LANEN
192PHY1_MDI1+I/OPHY1_MDI1+PHY1 MDI1 LANEP
194PHY1_LED2/CFG_LDO1OPHY1_LED2/CFG_LDO1PHY1_LED2/CFG_LDO1
196PHY1_MDI2-I/OPHY1_MDI2-PHY1 MDI2 LANEN
198PHY1_MDI2+I/OPHY1_MDI2+PHY1 MDI2 LANEP
200GNDGGNDDigital core Ground
202PHY1_MDI3-I/OPHY1_MDI3-PHY1 MDI3 LANEN
204PHY1_MDI3+I/OPHY1_MDI3+PHY1 MDI3 LANEP
206GPIO[5]_123 { MMC2_DAT[2] / SSPA1_FRM / UART6_RXD / R.UART0_RXD / PCIEB_PWRLED }AY24I/O1.8VMMC2_DAT2General purpose I/O5 123
208FAN_TACH(1V8)I1.8VFAN_TACHFAN TACH
210PMIC_32K_OUT(3V3)O1.8VPMIC_32K_OUTPMIC 32KHz Clock
212GPIO[3]_56 { GMAC2_INT_N / UART3_TXD / SSP0_FRM / R.UART3_TXD / PWM14 }J37I1.8VM2_ALERTGeneral purpose I/O3 56
214GPIO[3]_69 { R.GMAC3_TX_D3 / SSPA4_CLK / ESPI0_D1 / E/DP1_HPD / DSI0_TE / SSP3_RXD }H40I1.8VFORCE_RECOVERYGeneral purpose Strp I/O3 69
216GPIO[5]_125 { MMC2_DAT[0] / SSPA1_RXD / PCIED_WAKEN / E/DP1_HPD / PCIEB_EINTEG }AU23I/O1.8VMMC2_DAT0General purpose I/O5 125
218GPIO[5]_126 { MMC2_CMD / SSPA1_SYSCLK / PCIED_CLKREQN / I2C5_SCL }AV23I/O1.8VMMC2_CMDGeneral purpose I/O5 126
220GPIO[5]_101 { SSP3_SCLK / SSPA3_TXD / UART4_CTS / CAN4_RXD / PCIED_ATTN / MNCLK_OUT1 }AU28O1.8VI2S3_SDOUTI2S3_SDOUT
222GPIO[5]_102 { SSP3_FRM / SSPA3_RXD / UART4_RTS / CAN4_TXD / PCIED_PWRCTN / I2C1_SCL }AV28I1.8VI2S3_SDINI2S3_SDIN
224GPIO[5]_100 { SSP3_RXD / SSPA3_FRM / UART4_RXD / R.CAN2_RXD / PCIED_PRSNT2N / CLK32K_OUT }AT28I1.8VI2S3_LRCKI2S3_LRCK
226GPIO[5]_99 { SSP3_TXD / SSPA3_CLK / UART4_TXD / R.CAN2_TXD / CLK_CAMCK4 }AR28O1.8VI2S3_CLKI2S3_CLK
228GPIO[5]_127 { MMC2_CLK / PCIED_PRSNT2N / I2C5_SDA / USB30-2_DRV }AY23I/O1.8VMMC2_CLKGeneral purpose I/O5 127
230FAN_PWM(1V8)O1.8VFAN_PWMFAN PWM
232GPIO[3]_54 { GMAC2_MDC / UART3_RTSN / SSP0_RXD / PCIEA_EINTEG / I2C1_SCL / PWM12 }H38O1.8VI2C1_SCLI2C1_SCL
234GPIO[3]_55 { GMAC2_MDIO / UART3_RXD / SSP0_SCLK / R.UART3_RXD / I2C1_SDA / PWM13 }H37I/O1.8VI2C1_SDAI2C1_SDA
236PWR_SSP_SCLK { GPIO[122] / UART0_TXD }G40O1.8VUART0_TXD_PMUDebug UART0_TXD
238PWR_SSP_FRM { GPIO[123] / UART0_RXD }E36I1.8VUART0_RXD_PMUDebug UART0_RXD
240GPIO[4]_84 { SSP0_FRM / SSPA0_RXD / UART9_TXD / USB30-1_DRV / PCIEA_PWRCTN / DSI0_TE }AY34I/O3.3VSLEEP/WAKEGeneral purpose I/O4 84
242GNDGGGNDDigital core Ground
244GND
246GND
248GND
250GND
252VDD_IN(5V/20V)P5V/9~19VVDD_INK3-CoM260 Power
254VDD_IN(5V/20V)
256VDD_IN(5V/20V)
258VDD_IN(5V/20V)
260VDD_IN(5V/20V)

4. 电气、机械及热特性​

4.1 运行和最大额定值​

推荐操作条件​

SymbolParameterMinimumTypicalMaximumUnit
VDDDCVDD_IN (MODULE_ID low)4.7555.25V
VDD_IN (MODULE_ID high)12-20V
VCC_RTC1.85-5.5V

注意

现核心板设计仅支持高压（12 V～20 V）输入供电。载板设计须满足以下要求：

  1. 将 MODULE_ID（Pin 217）通过上拉电阻连接至 3.3 V。
  2. MODULE_ID 上拉电源必须先于 VDD_IN 建立，否则核心板可能无法正常启动。
  3. 如需 5 V 供电模式，请联系进迭时空。

绝对最大额定值​

SymbolParameterMinimumMaximumUnitNotes
VDDMAXVDD_IN (MODULE_ID low)-0.55.5V
VDD_IN (MODULE_ID high)-0.520.5V
VCC_RTC-0.37.0V
IDDMAXVDD_IN Imax-5A
VM_PIN施加到任何有电 I/O 引脚的电压-0.5VDD + 0.2V当 SYS_RESET* 为高电平且相关 I/O 电源已供电时为 VDD + 0.2。
SYS_RESET* 变为高电平之前，I/O 引脚不能为高电平（>0.5V）。
当 SYS_RESET* 为低电平时，施加在任何 I/O 引脚上的最大电压为 0.5V。
TOP工作温度-2070°C
TSTG存储温度TBDTBD°C

5. 包装​

此节提供了 K3-CoM260 包装信息。

TBD